(1) Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which has a function of entering a test mode when a voltage higher than a power source voltage is applied to an external terminal of the circuit.
(2) Description of the Related Art
In recent years, enhancement of the high integration of semiconductor integrated circuits has been and is proceeding, and this has led to progressively greater time required for a screening tests to distinguish between acceptable and defective products. This is a significant problem in the mass production of semiconductor integrated circuits. It is also a problem that, as the complication of semiconductor integrated circuits proceeds, circuit evaluation and analysis of defective products become more difficult. In most cases, as a countermeasure for the problems described above, various testing circuits are built into semiconductor integrated circuits in order to reduce the testing time or to facilitate circuit evaluation and analysis of defective products.
One methods of causing the testing circuit to enter a test mode in order to use a testing circuit is the super-voltage method wherein a voltage (hereinafter referred to as super-voltage) higher than a power source voltage by a fixed level or more is applied to a particular external terminal. In this instance, a super-voltage discriminating circuit to which the super-voltage is inputted outputs a testing circuit drive signal for activating the testing circuit.
FIG. 1 is a circuit diagram showing part of a semiconductor integrated circuit of the prior art to which the super-voltage method is applied. In this circuit configuration, a semiconductor integrated circuit 300 is a semiconductor storage device, and an address pin 35 is selected for application of a super-voltage. A first-stage input circuit 31 and a super-voltage discriminating circuit (hereinafter referred to simply as the discriminating circuit) 32 are connected to the address pin 35.
The first-stage input circuit 31 includes P-channel MOS transistor Tr5 and N-channel MOS transistor Tr6 which are connected so as to form a CMOS inverter, and N-channel MOS transistor Tr7 which connects the gate of N-channel MOS transistor Tr6 to the address pin 35. Transistor Tr7 drops a signal voltage applied to the gate of transistor Tr6. The first-stage input circuit 31 having the construction just described is disclosed in Japanese Patent Laid-Open No. Heisei 4-123388.
The discriminating circuit 32 includes a pair of N-channel MOS transistors Tr1 and Tr2 and P-channel MOS transistor Tr4 connected in series to the address pin 35, P-channel MOS transistor Tr3 which supplies the power source voltage to the gate of transistor Tr4, a resistor R having a high resistance and connecting the other end of transistor Tr4 to the ground, an inverter IV1 having an input end connected to a junction between transistor Tr4 and the resistor R, and another inverter IV2 having an input end connected to the output end of inverter IV1 and outputting a testing circuit drive signal SVT.
In order for drive signal SVT of discriminating circuit 32 to have the high level, it is necessary for voltage VG at the input end of inverter IV1 to be higher than the input threshold level of inverter IV1. Where the voltage drops by transistors Tr1, Tr2 and Tr4 in the ON state are represented by VT1, VT2 and VT4, respectively, and the power source voltage and the voltage of input signal AD are represented by VCC and VAD, respectively, voltage VG is represented by the following equation: EQU VG=VAD-VT1-VT2-VT3-VCC
(The resistance of resistor R is set to a sufficiently high value).
Accordingly, when the voltage of input signal AD is equal to or higher than a particular fixed level, drive signal SVT presents the high level, but when the voltage is lower than the particular fixed, level, drive signal SVT presents the low level.
Normally, voltage VAD at which drive signal SVT is changed over to the high level is set higher than an input pin applied voltage specified by the absolute maximum rated voltage in order to prevent unwanted entry into the testing mode. The high level of drive signal SVT is latched in response to a momentary super-voltage by a latch circuit (not shown) so that the super-voltage may be prevented from being applied for a long period of time, thereby preventing the otherwise possible destruction of the transistors.
FIG. 2 is a circuit diagram showing another example of a semiconductor integrated circuit of the prior art to which the super-voltage method is applied. In the semiconductor integrated circuit, an external terminal 37 is selected for application of a super-voltage.
Output circuit 33 includes a pair of N-channel MOS transistors Tr10 and Tr11 to which internal signals DTP and DTN are inputted by way of inverters IV5 and IV6, respectively. When signal DTP is at the high level and signal DTN is at the low level, output end D2 presents the low level, but when signal DTP is at the low level and signal DTN is at the high level, output end D2 presents the high level. 0n the other hand, when both signals DTP and DTN present the high level, output end D2 presents a high impedance state. Normally, a super-voltage is applied to the-external terminal 37 when output end D2 presents a high impedance state. The discriminating circuit 32 has the same configuration as that of FIG. 1 and outputs drive signal SVT to activate a testing circuit when it detects a super-voltage. When a super-voltage is applied to the external terminal 37, it is applied between the gates of transistors Tr10 and Tr11 and output end D2.
In any of the prior art semiconductor integrated circuits described above, the short-term application of a considerably high-voltage super-voltage to the particular external terminal may cause the problem that the high potential difference produced between the gate and drain D1 of P-channel MOS transistor Tr of the first-stage input circuit may destroy the gate oxide film constituting the transistors, as shown in the semiconductor integrated circuit shown in FIG. 1. This problem is becoming increasingly severe with the reduction of thickness of gate oxide film accompanying the recent increases in high integration.